| 摘要 |
A time register (300) includes: a pair of inputs (345, 346) coupled to a pair of input clocks (IN1, IN2); a pair of tri-state inverters (301, 302) for producing a pair of level signals (VC1, VC2); and a pair of outputs (347, 348) coupled to the level signals (VC1, VC2) for producing a pair of output clocks (OUT1, OUT2), wherein the tri-state inverters (301, 302) are responsive to a pair of state signals (S1, S2) and the pair of input clocks (IN1, IN2) for holding or discharging the level signals (VC1, VC2). |
