| 摘要 |
Partial decode logic 616 in a select stage of a pipelined multi-stage fetch unit 602 receives an instruction bundle from instruction cache 614. If a subroutine call and link instruction is identified in the bundle, the target address of the corresponding return instruction is predicted and pushed onto a return prediction stack (RPS) 604. In addition the target instruction set is also predicted and pushed onto RPS 604 alongside the target address. The target set is that pointed to by the target address, e.g. the bundle following the subroutine call in the program and currently being fetched in cache stage 608. When the partial decode logic identifies a return instruction, the target set is popped from the RPS to be decoded. This way a cycle is not wasted re-fetching the target set in response to detecting the return instruction, reducing pipeline bubbles due to control transfer instructions. |
