Pulse-drive resonant clock with on-the-fly mode change

摘要

A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

主权项

1. A clock driver circuit for a resonant clock distribution network, the clock driver circuit comprising:
at least one clock driver output stage having an output for driving a drive point of a sector of the resonant clock distribution network, having a clock input coupled to a global clock signal, and having a first enable input for enabling and disabling a pull-up driver of the at least one clock driver output stage and a second enable input for enabling and disabling a pull-down driver of the at least one clock driver output stage; a delay line having a selectable delay selected in conformity with a mode select input and further having an input for receiving the global clock signal, wherein the delay line further includes a mode select control logic responsive to the mode select input; and a clock pulse width control logic having a first output coupled to the first enable input of the clock driver output stage, a second output coupled to the second enable input of the clock driver output stage and an input coupled to an output of the delay line, wherein the clock pulse width control logic enables the at least one clock driver output stage in response to changes in state of global clock signal and disables the at least one clock driver output stage when the changes in state of the global clock signal have propagated through the delay line, and wherein the mode select control logic prevents the clock pulse width control logic from enabling the at least one clock driver output stage for a duration shorter than a delay time of the delay line when the mode select input changes state.