发明名称 Input path matching in pipelined continuous-time analog-to-digital converters
摘要 System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
申请公布号 US9614510(B2) 申请公布日期 2017.04.04
申请号 US201615068231 申请日期 2016.03.11
申请人 Texas Instruments Incorporated 发明人 Srinivasan Venkatesh;Shi Kun;Wang Victoria;Klemmer Nikolaus
分类号 H03K5/159;H03M3/00;H03M1/16 主分类号 H03K5/159
代理机构 代理人 Kondapalli Goutham;Brill Chares A.;Cimino Frank D.
主权项 1. A method comprising: comparing magnitude and phase of a coarse resolution signal path of a first stage sub-analog-to-digital converter (sub-ADC) in a pipelined continuous-time analog-to-digital converter (CT ADC) with magnitude and phase of a continuous-time signal path of the pipelined CT ADC to generate a residue magnitude and phase, using the continuous-time signal path comprising an input delay circuit, the residue magnitude and phase generated by a first summing circuit; and varying a delay value of at least one digital delay circuit for reducing the residue magnitude and phase, the at least one digital delay circuit positioned at an output of the first stage sub-ADC and coupled to each of the first summing circuit and a second summing circuit, the second summing circuit positioned at an output of a second stage sub-ADC, the second stage sub-ADC coupled to an output of the first summing circuit.
地址 Dallas TX US