发明名称 |
Method for simultaneous structuring and chip singulation |
摘要 |
A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions. |
申请公布号 |
US9610543(B2) |
申请公布日期 |
2017.04.04 |
申请号 |
US201414170187 |
申请日期 |
2014.01.31 |
申请人 |
Infineon Technologies AG |
发明人 |
Grille Thomas;Hedenig Ursula;Roesner Michael;Stranzl Gudrun;Zgaga Martin |
分类号 |
H01L21/00;B01D67/00;B81C1/00 |
主分类号 |
H01L21/00 |
代理机构 |
Slater Matsil, LLP |
代理人 |
Slater Matsil, LLP |
主权项 |
1. A method comprising:
providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface; performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, wherein the plurality of individual semiconductor chips comprises at least one of membrane filters, sieves, grids, hole plates, and pressure impulse attenuators; and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions. |
地址 |
Neubiberg DE |