发明名称 Method for fabricating semiconductor package and semiconductor package using the same
摘要 Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.
申请公布号 US9613829(B1) 申请公布日期 2017.04.04
申请号 US201615148895 申请日期 2016.05.06
申请人 AMKOR TECHNOLOGY, INC. 发明人 Lee Seung Woo;Kim Byong Jin;Bang Won Bae;Kang Sang Goo
分类号 H01L29/84;H01L21/48;H01L23/31;H01L23/495;H01L23/522;H01L21/56 主分类号 H01L29/84
代理机构 McAndrews, Held & Malloy, Ltd. 代理人 McAndrews, Held & Malloy, Ltd.
主权项 1. A method for fabricating a semiconductor package, the method comprising: forming a first leadframe pattern; encapsulating the first leadframe pattern with an encapsulant defining: an encapsulant first surface adjacent the first leadframe pattern; andan encapsulant second surface opposite the encapsulant first surface; forming a conductive via extending from the encapsulant second surface to the first leadframe pattern; forming a second leadframe pattern on the encapsulant second surface, the second leadframe pattern coupled to the first leadframe pattern through the conductive via; etching part of the first leadframe pattern to form an etched first leadframe surface configured to receive an interconnect to a semiconductor die; and one or both of: forming a first solder mask on the encapsulant second surface and exposing a portion of the second leadframe pattern; and/orforming a second solder mask on the encapsulant first surface and exposing a portion of the etched first leadframe surface.
地址 Tempe AZ US