| 发明名称 | Memory device including decoder for a program pulse and related methods | ||
| 摘要 | An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse. | ||
| 申请公布号 | US9613696(B1) | 申请公布日期 | 2017.04.04 |
| 申请号 | US201514971345 | 申请日期 | 2015.12.16 |
| 申请人 | STMICROELECTRONICS INTERNATIONAL N.V.;STMICROELECTRONICS S.R.L. | 发明人 | Pasotti Marco;Carissimi Marcella;Rana Vikas |
| 分类号 | G11C11/00;G11C13/00 | 主分类号 | G11C11/00 |
| 代理机构 | Slater Matsil, LLP | 代理人 | Slater Matsil, LLP |
| 主权项 | 1. An integrated circuit comprising: an array of phase-change memory (PCM) cells; a plurality of bitlines coupled to the array of PCM cells; a first decoder circuit comprising a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell from among the array thereof; and a second decoder circuit comprising a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse. | ||
| 地址 | Amsterdam NL | ||