Switch circuit to control the flow of charges in the parasitic capacitance of a TFT in the pixel of a display

摘要

The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes: a plurality of data lines and a plurality of gate lines configured to divide a display region into a plurality of display sub-regions; a pixel electrode arranged at each display sub-region; and a TFT arranged at each display sub-region, a source electrode of the TFT being electrically connected to the data line, a drain electrode thereof being electrically connected to the pixel electrode and a gate electrode thereof being electrically connected to the gate line, wherein a parasitic capacitor is formed between the gate electrode and the drain electrode of the TFT. The array substrate further includes a switch circuit configured to enable both ends of the parasitic capacitor to be electrically connected when a gate driving signal of the TFT is changed from a high level to a low level.

主权项

1. An array substrate, comprising:
a plurality of data lines and a plurality of gate lines, configured to divide a display region into a plurality of display sub-regions; a pixel electrode arranged at each display sub-region; and a TFT arranged at each display sub-region, a source electrode of the TFT being electrically connected to the data line, a drain electrode of the TFT being electrically connected to the pixel electrode and a gate electrode of the TFT being electrically connected to the gate line, wherein a parasitic capacitor is formed between the gate electrode and the drain electrode of the TFT, and the array substrate further comprises: a switch circuit configured to enable both ends of the parasitic capacitor to be electrically connected when a gate driving signal of the TFT is changed from a high level to a low level, wherein the switch circuit comprises: a first switch unit arranged at at least one display sub-region, and connected in parallel to the parasitic capacitor formed on the TFT at the corresponding display sub-region; and a second switch unit arranged in correspondence with the first switch unit, wherein one end of a parallel circuit formed by the parasitic capacitor and the first switch unit is electrically connected to the drain electrode of the TFT, and another end of the parallel circuit is electrically connected to the gate electrode of the TFT via the second switch unit, and the first switch unit is in the ON state and the second switch unit is in the OFF state when the gate driving signal of the TFT at the corresponding display sub-region is changed from a high level to a low level.