发明名称 Internal/external clock selection circuit and method of operation
摘要 A clock circuit includes an amplifier, an electrical supply, a feedback circuit, and a comparator. The amplifier has an input node and an output node that are coupled to a crystal to provide an internal clock signal on the output node at a specified frequency. The electrical supply source provides electrical power to the amplifier at a specified input voltage. The feedback circuit is coupled between the input node and the output node, and forms a low pass filter for attenuating the internally generated clock signal on the input node. The feedback circuit biases the input node at a direct current (DC) voltage level that is biased to be less than the specified input voltage. When an external clock signal is applied at the output node, the comparator generates a digital clock signal according to the external clock signal, and when no external clock signal is applied at the output, the comparator generates the digital clock signal according to the internal clock signal.
申请公布号 US9614509(B1) 申请公布日期 2017.04.04
申请号 US201615181076 申请日期 2016.06.13
申请人 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC 发明人 Ahmed Abdullah
分类号 H03K3/00;H03K5/15;H03B5/32;H03K5/00 主分类号 H03K3/00
代理机构 Conley Rose, P.C. 代理人 Conley Rose, P.C.
主权项 1. A clock circuit comprising: an amplifier having an input node and an output node that are coupled to a crystal to provide an internal clock signal on the output node at a specified frequency; an electrical supply source providing electrical power to the amplifier at a specified input voltage; a feedback circuit coupled between the input node and the output node, the feedback circuit forming a low pass filter for attenuating the internally generated clock signal on the input node; and a comparator having a first comparator input coupled to the output node and a second comparator input coupled to the output node, wherein the feedback circuit biases the input node at a direct current (DC) voltage level that is biased to be less than the specified input voltage such that: when an external clock signal is applied at the output node of the amplifier, the comparator generates a digital clock signal according to the external clock signal, andwhen no external clock signal is applied at the output, the comparator generates the digital clock signal according to the internal clock signal.
地址 Phoenix AZ US