发明名称 III-Nitride semiconductors with recess regions and methods of manufacture
摘要 A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride material, a barrier layer comprising a second III-Nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess. The filler element, comprising an insulating material, is disposed at least below the bottom step of the gate electrode within the gate recess. Also described are methods for fabricating such semiconductor structures. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
申请公布号 US9614069(B1) 申请公布日期 2017.04.04
申请号 US201615376826 申请日期 2016.12.13
申请人 Cambridge Electronics, Inc. 发明人 Lu Bin;Xia Ling
分类号 H01L21/336;H01L27/088;H01L29/778;H01L29/20;H01L29/205;H01L29/66 主分类号 H01L21/336
代理机构 American Patent Agency PC 代理人 American Patent Agency PC ;Hussain Daniar;Shi Xiaomeng
主权项 1. A method of fabricating a multi-layer semiconductor structure for use in a III-Nitride (III-N) semiconductor device, comprising: forming a channel layer comprising a first III-N material for providing electrical conduction; forming a barrier layer comprising a second III-N material above the channel layer, wherein the barrier layer comprises a band-offset layer, wherein the band-offset layer comprises a third III-N material, and wherein the band-offset layer has a wider bandgap than the channel layer; forming a pair of ohmic recesses by patterning and etching of the barrier layer; depositing a pair of ohmic electrodes in the pair of ohmic recesses respectively; forming a gate recess by patterning and etching of the barrier layer, wherein the gate recess is positioned in-between the pair of ohmic recesses; depositing a first filler layer covering a bottom of the gate recess, wherein the first filler layer comprises a first insulating material; recessing a recess through the first filler layer, wherein a length of the recess through the first filler layer is smaller than that of the gate recess, to form a first filler element at a bottom of the gate recess; and depositing a gate electrode in the gate recess, wherein the gate electrode is stepped by the first filler element to form a bottom stem and a bottom step within the gate recess.
地址 Cambridge MA US
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