Supplemental write cache command for bandwidth compression

摘要

Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.

主权项

1. A method for executing cache memory access requests for data on a computing device, comprising:
receiving, by a cache memory controller from a processor, a cache memory access request for data smaller than a cache line to which the data is addressed in the cache memory access request; receiving, by the cache memory controller from the processor, a supplemental write command associated with the received cache memory access request; determining whether the data requested by the cache memory access request is smaller than a cache line in response to receiving both the cache memory access request and the supplemental write command; and writing supplemental data to unfilled portions of the cache line to which the data is addressed in the cache memory access request.