RF power multi-chip module package

摘要

High power multi-chip module packages for packaging semiconductor dice are disclosed. The disclosed packages have an output power of at least 1 kilowatt (kW) and can have an operating signal frequency in a range of hundreds of MHz. The high power multi-chip module packages have base plates with multiple planes or layers that can be conductive and may be thin metal layers in some examples. The multiple planes are formed and overlaid in such a way that they help reduce stray inductance values caused by the packaging itself, which improves overall device operation and efficiency. Current loops created when one of the multi-chip modules is in a turn-on condition are balanced and opposed and generate a minimized B-Field that is restricted by the manner in which the multiples planes of the base plate are overlaid, thus reducing the stray inductance values and improving device operation.

主权项

1. A base plate for a high power multi-chip module package having a power output of at least 1 kilowatt (kW) and an operating signal frequency in the range of up to hundreds of MHz, comprising:
a low side switch (LSS) plane having an LSS protrusion; a positive supply voltage (PSV) plane having a first recession and a second recession, the first recession configured to receive the LSS protrusion and cause the LSS plane and the PSV plane to be intermingled; and a high side switch (HSS) plane, a portion of the HSS plane placed over a portion of the PSV plane, the HSS plane having an HSS protrusion structured to intermingle with the second recession of the PSV plane, the HSS plane placed over the portion of the PSV plane to define an HSS-PSV plane edge; and an open gap defined between an intermingled edge of the LSS plane and the HSS-PSV plane edge; wherein at a turn-on condition for multiple transistor dies mounted to the base plate, transistor die driver current loops are created by currents flowing between the multiple transistor dies and respective multiple transistor die drivers that are balanced and opposed, and output current loops are created by currents flowing from the multiple transistor dies to an output destination that are also balanced and opposed.