Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems

摘要

Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.

主权项

1. A method, comprising:
generating a test case for a plurality of processors, wherein the test case comprises streams of instructions; allocating at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line; pairing a first subset of the streams of instructions of the generated test case; scheduling the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors, wherein a first subset of the streams of instructions is executed by a first one or more processors of the plurality of processors; and re-scheduling the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors, wherein the first subset of the streams of instructions is re-scheduled for execution by a second one or more processors of the plurality of processors without waiting for any other processors except the first one or more processors to finish executing the first subset of the streams of instructions.