Nonvolatile semiconductor memory device

摘要

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

主权项

1. A nonvolatile semiconductor memory device comprising:
a cell unit including a first selection gate transistor and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and including a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to execute writing data to the memory cells, the writing data having one or more program stages, wherein the memory cells include a first memory cell, to be executed an M1-stage program, M1=an integer of 1 or more, a second memory cell, to be executed an M2-stage program, M2=an integer larger than M1 and being nearer to the first selection gate transistor than the first memory cell, and a third memory cell, to be executed the M2-stage program and being nearer to the first selection gate transistor than the second memory cell, and the data write circuit:
executes the m2-th stage program, m2=an integer of 1 to M2, to the second memory cell after execution of the m2-th stage program to the third memory cell,executes the m1-th stage program, m1=an integer of 1 to M1, to the second memory cell,executes the (m1+1)-th stage program to the second memory cell after execution of the mi-th stage program to the second memory cell, andexecutes the mi-th stage program to the first memory cell after execution of the (m1+1)-th stage program to the second memory cell.