Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods

摘要

Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

主权项

1. A memory system for a processor-based system, comprising:
a memory; a memory controller configured to:
periodically power-up during idle periods of a processor;generate a power-up signal indicating a powered-up state of the memory controller;respond to requests from the processor to perform memory transactions to the memory in response to the powered-up state; andgenerate the power-up signal indicating a powered-down state of the memory controller in response to an idle period of the processor; and a memory data scrubber circuit configured to:
receive the power-up signal from the memory controller; andperform a memory data scrubbing operation on at least one next scrubbing memory address in the memory in response to receiving the power-up signal from the memory controller and independent of the powered-down state of the memory controller.