MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION

摘要

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

主权项

1. A memory device including an error correction code (ECC) circuit, the memory device comprising:
a memory cell array configured to store data bits, each of the memory cells in the memory cell array being connected to a word line and a bit line respectively and being selected by an address applied from outside during write and/or read operation; an ECC cell array configured to store parity bits, each of the ECC cells in the ECC cell array having the same cell structure as each memory cell and being connected to a word line and a bit line respectively; a fail address storing unit configured to store fail addresses, the fail addresses including a first fail address and a second fail address, the first fail address and the second fail address indicating a first type of fail cells and a second type of fail cells respectively; a control logic unit configured to compare the first fail address and the second fail address with the address applied from outside and generate a first control signal if the first fail address matches with the address applied from outside and generate a second control signal if the second fail address matches with the address applied from outside; and an ECC circuit configured to perform an ECC operation on the memory cell array, the ECC circuit performing an ECC operation by using [m, n] Hamming codes with respect to n data bits, m being the size of a codeword which is a sum of the number of parity bits and the number of data bits, wherein the ECC circuit changes size of the codeword in response to the control signals.