Instruction and Logic for Indirect Accesses

摘要

A processor includes a cache, a front end to decode an instruction, execution units to execute the instruction, and a retirement unit to retire the instruction. The instruction specifies that a vector of data will be prefetched. The instruction is to include a mask, the mask is to indicate whether corresponding values of the vector of data are included within the cache. The execution units include logic to issue prefetches for each value of the vector of data for which the mask indicates that is unavailable within the cache, and logic to suppress prefetches for each value of the vector of data for which the mask indicates that is available within the cache.

主权项

1. A processor, comprising:
a cache; a front end including a decoder to decode a first instruction, the first instruction to specify that a vector of data will be prefetched and to include a mask, the mask to indicate whether corresponding values of the vector of data are included within the cache; one or more execution units to execute the first instruction, including;
a first logic to issue prefetches for each value of the vector of data for which the mask indicates that is unavailable within the cache; anda second logic to suppress prefetches for each value of the vector of data for which the mask indicates that is available within the cache; and a retirement unit to retire the first instruction.