APPARATUS AND METHOD FOR FLOATING-POINT MULTIPLICATION

摘要

An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands, which are then added to generate a product significand. The value of an unbiased result exponent is determined from the operand exponent values and leading zero counts, and a shift amount and direction for the product significand are determined in dependence on a predetermined minimum exponent value of a predetermined canonical format. The product significand is shifted by the shift amount in the shift direction. An overflow mask identifying an overflow bit position of the product significand is generated by right shifting a predetermined mask pattern by the shift amount, and the overflow mask is applied to the product significand to extract an overflow value at the overflow bit position. This extraction of the overflow value happens before the shift circuitry shifts the product significand, allowing an overall faster floating-point multiplication to be performed.

主权项

1. Apparatus for floating-point multiplication comprising:
partial product generation circuitry to multiply significands of a first floating-point operand and a second floating-point operand to generate first and second partial products; adder circuitry to add the first and second partial products to generate a product significand; exponent calculation circuitry to calculate a value of an unbiased exponent of a result of the multiplication in dependence on exponent values and leading zero counts of the first and second floating-point operands and to determine a shift amount and a shift direction for the product significand in dependence on a predetermined minimum exponent value of a predetermined canonical format; shift circuitry to shift the product significand by the shift amount in the shift direction in order to generate a formatted significand in the predetermined canonical format; mask generation circuitry to generate an overflow mask identifying an overflow bit position of the product significand, wherein the mask generation circuitry is arranged to generate the overflow mask by right shifting a predetermined mask pattern by the shift amount; and comparison circuitry to apply the overflow mask to the product significand to extract an overflow value at the overflow bit position, wherein the comparison circuitry is arranged to extract the overflow value before the shift circuitry shifts the product significand.