| 摘要 |
Apparatus and methods for fractional-N synthesizer phase-locked loops with multi-phase oscillators are provided. In certain configurations, a fractional-N PLL includes a time- to-digital converter (TDC), a digital loop filter, a multi-phase oscillator, and fractional division circuitry. The multi-phase oscillator includes multiple taps used to generate multiple clock signal phases that are provided to the fractional division circuitry to reduce the fractional-N PLL's quantization error. The fractional division circuitry includes a tap error correction circuit for compensating for errors in tap positions of the multi-phase oscillator. By including the tap error correction circuit, the phase noise and/or jitter performance of the fractional-N PLL can be enhanced. |
