| 发明名称 |
DOUBLE AFFINE MAPPED S-BOX HARDWARE ACCELERATOR |
| 摘要 |
A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence |
| 申请公布号 |
US2017093571(A1) |
申请公布日期 |
2017.03.30 |
| 申请号 |
US201514863769 |
申请日期 |
2015.09.24 |
| 申请人 |
Intel Corporation |
发明人 |
SATPATHY SUDHIR K.;MATHEW SANU K.;GOPAL VINODH;YAP KIRK S. |
| 分类号 |
H04L9/10 |
主分类号 |
H04L9/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processing system, comprising:
a memory; a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module to implement a byte substitute operation by performing:
a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence,an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, anda second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence. |
| 地址 |
Santa Clara CA US |
