SHIFT REGISTER AND DRIVING METHOD THEREOF, AND GATE DRIVING CIRCUIT

摘要

A shift register, a driving method thereof, and a gate driving circuit. The shift register includes a first transistor, with a control terminal thereof electrically connected to a first control node; a scan driving unit; a reset unit; a maintaining control unit; a first potential maintaining unit, with a control terminal thereof electrically connected to a second control node, an input terminal thereof electrically connected to a third level signal line, and an output terminal thereof electrically connected to the first control node; and a second potential maintaining unit, with a first control terminal thereof electrically connected to the second control node, a second control terminal thereof electrically connected to a second clock signal line, an input terminal thereof electrically connected to a fourth level signal line, and an output terminal thereof electrically connected to the output terminal of the shift register.

主权项

1. A shift register, comprising:
a first transistor, wherein a gate of the first transistor is electrically connected with a first control node, a first electrode of the first transistor is electrically connected with a scanning signal input line, and a second electrode of the first transistor is electrically connected with an output terminal of the shift register; a scan driving unit, wherein a control terminal of the scan driving unit is electrically connected with an output terminal of a preceding N-th shift register, an input terminal of the scan driving unit is electrically connected with a first level signal line, and an output terminal of the scan driving unit is electrically connected with the first control node to control a potential of the first control node to turn on the first transistor and output a scanning signal, wherein N is a positive integer; a reset unit, wherein a control terminal of the reset unit is electrically connected with an output terminal of a succeeding M-th shift register, an input terminal of the reset unit is electrically connected with a second level signal line, and an output terminal of the reset unit is electrically connected with the first control node to control the potential of the first control node to turn off the first transistor, wherein M is a positive integer; a maintaining control unit, wherein a control terminal of the maintaining control unit is electrically connected with the first control node, a first input terminal of the maintaining control unit is electrically connected with a third or fourth level signal line, a second input terminal of the maintaining control unit is electrically connected with a first clock signal line, and an output terminal of the maintaining control unit is electrically connected with a second control node to control a potential of the second control node; a first potential maintaining unit, wherein a control terminal of the first potential maintaining unit is electrically connected with the second control node, an input terminal of the first potential maintaining unit is electrically connected with the third level signal line, and an output terminal of the first potential maintaining unit is electrically connected with the first control node; and a second potential maintaining unit, wherein a first control terminal of the second potential maintaining unit is electrically connected with the second control node, a second control terminal of the second potential maintaining unit is electrically connected with a second clock signal line, an input terminal of the second potential maintaining unit is electrically connected with a fourth level signal line, and an output terminal of the second potential maintaining unit is electrically connected with the output terminal of the shift register; wherein a polarity of a level signal outputted from the third level signal lines is identical to a polarity of a level signal outputted from the fourth level signal line, and an absolute value of the level signal outputted from the third level signal lines is greater than an absolute value of the level signal outputted from the fourth level signal line.