发明名称 Interface Apparatus for Semiconductor Testing and Method of Manufacturing Same
摘要 In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus includes a housing. The housing includes a lower housing substrate and an upper housing substrate. The lower housing substrate has a plurality of apertures arranged according to a fine pitch, and the upper housing substrate has a plurality of apertures arranged according to a coarse pitch. A plurality of wires passes through the plurality of apertures from the lower housing substrate to the upper housing substrate. Each wire has plated conductive ends emanating from opposing sides of the housing. The plurality of apertures of the lower housing substrate corresponds to the plurality of apertures of the upper housing substrate. The interface apparatus transforms a pattern having a course pitch to a pattern having a fine pitch.
申请公布号 US2017093101(A1) 申请公布日期 2017.03.30
申请号 US201514864823 申请日期 2015.09.24
申请人 Dau Hai;Weng Lim Hooi;Shanmugam Kothandan;Bui Christine 发明人 Dau Hai;Weng Lim Hooi;Shanmugam Kothandan;Bui Christine
分类号 H01R27/02;H01R43/20;H01R43/02 主分类号 H01R27/02
代理机构 代理人
主权项 1. An interface apparatus for semiconductor testing, said interface apparatus comprising: a housing including a first housing substrate having a first plurality of apertures arranged according to a first pitch, anda second housing substrate mated to said first housing substrate and having a second plurality of apertures arranged according to a second pitch; and a plurality of wires passing through said first and second plurality of apertures, each wire of said plurality of wires having plated conductive ends emanating from opposing sides of said housing, wherein said first plurality of apertures corresponds to said second plurality of apertures, and wherein said first pitch is less than said second pitch.
地址 San Ramon CA US