A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
申请公布号
WO2017052536(A1)
申请公布日期
2017.03.30
申请号
WO2015US51729
申请日期
2015.09.23
申请人
INTEL CORPORATION
发明人
CHANDHOK, Manish;YOUNKIN, Todd R.;HAN, Eungnak;CHAWLA, Jasmeet S. (JZ);KRYSAK, Marie;YOO, Hui Jae;TRONIC, Tristan A.
