发明名称 PCIE ERROR REPORTING AND THROTTLING
摘要 Examples described herein include an error report throttling mechanism for Peripheral Component Interconnect Express (PCIe) systems. The throwing mechanism updates an interrupt for the first port, and selectively performs an interrupt routine, in response to detecting the error message, based at least in part on the interrupt count for the first port. For example, the throwing mechanism may compare the interrupt count with a reporting threshold to determine whether an error reporting limit has been exceeded for the first port. Upon determining that the error reporting limit has been reached, the throttling mechanism may disable the interrupt routine for subsequent error messages received at the first port.
申请公布号 US2017091013(A1) 申请公布日期 2017.03.30
申请号 US201514868262 申请日期 2015.09.28
申请人 NetApp, Inc. 发明人 Tallam Sreenivas;Bachu David;Doddegowda Madhu;Thekkedath Gopakumar;Medavaram Dinakar
分类号 G06F11/07 主分类号 G06F11/07
代理机构 代理人
主权项 1. A method of error reporting in a Peripheral Component Interconnect Express (PCIe) system, the method comprising: detecting an error message at a first port of a root complex of the PCIe system; updating an interrupt count for the first port; and selectively performing an interrupt routine, in response to detecting the error message, based at least in part on the interrupt count for the first port.
地址 Sunnyvale CA US
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