INTEGRATED CIRCUIT WITH SECURE SCAN ENABLE

摘要

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.

主权项

1. An integrated circuit, comprising:
a plurality of registers configured to be connected in two or more scan chains for scan-testing the integrated circuit in response to a scan-enable signal being asserted; and a security-warning generator, connected to the two or more scan chains, that asserts a security-warning signal in response to the scan-enable signal being asserted at a first subset of the two or more scan chains, wherein the integrated circuit is configurable to prevent data from being read from at least some of the registers in response to the security-warning signal being asserted by the security-warning generator.