发明名称 HYBRID PITCH PACKAGE WITH ULTRA HIGH DENSITY INTERCONNECT CAPABILITY
摘要 A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
申请公布号 US2017092575(A1) 申请公布日期 2017.03.30
申请号 US201615370432 申请日期 2016.12.06
申请人 Intel Corporation 发明人 Manusharow Mathew J.;Sobieski Daniel N.;Roy Mihir K.;Lambert William J.
分类号 H01L23/498;H01L23/00;H05K1/16;H01L21/48 主分类号 H01L23/498
代理机构 代理人
主权项 1. A method of forming a hybrid pitch package comprising: obtaining a package having standard package pitch sized features above and below a layer of the package (1) in a standard package pitch sized zone of the package and (2) in a smaller processor pitch sized zone of the package that is adjacent to the standard package pitch sized zone of the package; then forming a protective mask over the standard package pitch sized zone of the package; and then forming smaller processor pitch sized features above the layer of the package in the smaller processor pitch sized zone, wherein the smaller processor pitch sized features have a pitch at least three times smaller than that of the standard package pitch sized features.
地址 Santa Clara CA US