SYSTEM AND PROCESS FOR SIMULATING THE BEHAVIORAL EFFECTS OF TIMING VIOLATIONS BETWEEN UNRELATED CLOCKS

摘要

According to one aspect, embodiments of the invention provide a CDC simulation system comprising a timing analysis module configured to receive a circuit design, analyze the circuit design to identify at least one CDC, and generate a report including information related to the at least one CDC, a CDC simulation module configured to communicate with the timing analysis module and to receive the report from the timing analysis module, and a test bench module configured to communicate with the CDC simulation module, to receive the circuit design, and to operate a test bench code to simulate the operation of the circuit design, wherein the CDC simulation module is further configured to edit a top level of the test bench code, based on the received report, such that the test bench module is configured to identify timing violations in the circuit design due to the at least one CDC.

主权项

1. A Clock Domain Crossing (CDC) simulation system comprising:
an interface configured to communicate with an external system and to receive a Behavioral Description Language (BDL) based circuit design from the external system; a timing analysis module configured to receive the BDL based circuit design from the interface, analyze the BDL based circuit design to identify at least one CDC within the circuit design, and generate a report including information related to the at least one CDC; a CDC simulation module configured to communicate with the timing analysis module and to receive the report from the timing analysis module; and a test bench module configured to communicate with the CDC simulation module and the interface, to receive the BDL based circuit design from the interface, and to operate a test bench code to simulate the operation of the BDL based circuit design, wherein the CDC simulation module is further configured to edit a top level of the test bench code, based on the received report, such that the test bench module is configured to identify timing violations in the BDL based circuit design due to the at least one CDC.