| 发明名称 |
LOW DENSITY PARITY CHECK DECODER |
| 摘要 |
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message. |
| 申请公布号 |
US2017093429(A1) |
申请公布日期 |
2017.03.30 |
| 申请号 |
US201615373822 |
申请日期 |
2016.12.09 |
| 申请人 |
The Texas A&M University System |
发明人 |
GUNNAM Kiran Kumar;CHOI Gwan S. |
| 分类号 |
H03M13/11;H03M13/00 |
主分类号 |
H03M13/11 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A low density parity check (LDPC) decoder, comprising:
LDPC decoding circuitry comprising:
a Q message generator that combines an R message from a previous iteration with a P message to produce a Q message; anda P sum adder array that adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message. |
| 地址 |
College Station TX US |
