FULL ADDRESS COVERAGE DURING MEMORY ARRAY BUILT-IN SELF TEST WITH MINIMUM TRANSITIONS

摘要

Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

主权项

1. In a memory, a method comprising:
arranging a plurality of addresses of a memory array as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array; selecting a current location in the matrix, wherein a column of the current location corresponds to a destination address of a memory transition, wherein the destination addresses identifies a candidate row of the matrix which corresponds to the destination address, wherein the candidate row is different from a row of the current location; determining a next location that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row; recording the next location; and performing a read access to an address of the memory array corresponding to a row of the next location.