发明名称 MEMORY WITH HIGH OVERLAY TOLERANCE
摘要 An embodiment includes an apparatus comprising: a first via layer between a substrate and a first metal layer; a second via layer between the first metal layer and second metal layer; a third via layer between the second metal layer and a third metal layer; and first and second access transistors each included in the substrate; wherein (a) the second via layer and the second metal layer each include portions of a first magnetic tunnel junction (MTJ) and portions of a second MTJ, (b) the third via layer includes a metal interconnect directly contacting the first and second MTJs, and (c) the third metal layer includes a bit line that couples to the first and second access transistors through the metal interconnect and the first and second MTJs. Other embodiments are described herein.
申请公布号 WO2017052561(A1) 申请公布日期 2017.03.30
申请号 WO2015US52032 申请日期 2015.09.24
申请人 INTEL CORPORATION 发明人 LEE, Kevin J.;WANG, Yih
分类号 H01L43/02;H01L43/10;H01L43/12 主分类号 H01L43/02
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