FETCH UNIT FOR PREDICTING TARGET FOR SUBROUTINE RETURN INSTRUCTIONS

摘要

A fetch unit configured to, in response to detecting a subroutine call and link instruction, calculate and store a predicted target address for the corresponding subroutine return instruction in a prediction stack, and if certain conditions are met, also cause to be stored in the prediction stack a predicted target instruction bundle. The fetch unit is also configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and if certain conditions are met, cause any valid predicted target instruction bundle in the prediction stack to be the next bundle to be decoded.

主权项

1. A multi-stage fetch unit for use in a processor, the multi-stage fetch unit comprising:
a return prediction stack; and partial decode logic in communication with the return prediction stack, the partial decode logic configured to, in a cycle:
receive a set of one or more instructions for execution;at least partially decode the received set of one or more instructions to determine whether the received set of one or more instructions comprises a subroutine call and link instruction or a subroutine return instruction;in response to determining that the received set of one or more instructions comprises a subroutine call and link instruction, cause a predicted target set of one or more instructions for a corresponding subroutine return instruction to be stored in the return prediction stack; andin response to determining that the received set of one or more instructions comprises a subroutine return instruction, cause a predicted target set of one or more instructions stored in the return prediction stack to be the received set of one or more instructions in a next cycle.