SYSTEM AND METHOD FOR DUTY CYCLE CORRECTION

摘要

Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.

主权项

1. An apparatus comprising:
a duty cycle corrector (DCC) configured to receive an input clock signal and a control signal and to produce an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit configured to divide a frequency of the input clock signal by N and to generate an intermediate clock signal, wherein N being an integer more than 1; and a phase detector configured to generate the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.