| 主权项 |
1. A chip package, comprising:
a first redistribution layer (RDL); a first chip comprising a plurality of first contact pads on a first surface of the first chip, the plurality of first contact pads facing the first RDL; a second RDL over and contacting the first surface of the first chip, the second RDL being coupled to the plurality of first contact pads and having a same width with the first chip; a second chip comprising a plurality of second contact pads on a first surface of the second chip, the plurality of second contact pads facing the first RDL, the second chip being laterally adjacent to the first chip; a third RDL over and contacting the first surface of the second chip, the third RDL being coupled to the plurality of second contact pads and having a same width with the second chip, wherein the second RDL is laterally separated from the third RDL with a molding compound disposed therebetween; a third chip disposed between the first chip and the first RDL, the third chip interposed between the second chip and the first RDL, wherein a portion of the first chip is disposed outside a lateral extent of the third chip, wherein a portion of the second chip is disposed outside the lateral extent of the third chip, and wherein the third chip comprises a plurality of third contact pads facing the first RDL; and a conductive via laterally separated from the third chip, the conductive via extending between the first RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the third chip, wherein an end of the conductive via adjacent to the first RDL is coplanar with pillars on the plurality of third contact pads of the third chip. |
