发明名称 SCALED INTERCONNECT VIA AND TRANSISTOR CONTACT BY ADJUSTING SCATTERING
摘要 Described is an apparatus which comprises: a via formed of a first material; and a first interconnect, formed of a second material, with an end region coupled to the via, wherein the first interconnect has an angled sidewall at the end region. Described is an apparatus which comprises: a via formed of a first material; and a first interconnect, formed of a second material, with an end region coupled to the via, wherein the first interconnect has a rougher interface for at least one wall of the first interconnect at the end region compared to at least another wall of the first interconnect.
申请公布号 WO2017052654(A1) 申请公布日期 2017.03.30
申请号 WO2015US52483 申请日期 2015.09.25
申请人 INTEL CORPORATION 发明人 AVCI, Uygar E.;YOUNG, Ian A.
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
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