Instruction and Logic for Interrupt and Exception Handling

摘要

A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.

主权项

1. A processor, comprising:
a processor trace logical unit (PTLU), including a first logic to produce branch execution records from execution of instructions; a second logic to determine that a condition, the condition to include an asynchronous event or a return from a software handler for an asynchronous event, has occurred on the processor during execution of the instructions; a third logic to determine whether event tracing is enabled for the processor; a fourth logic to generate a control flow event (CFE) packet, the CFE packet to indicate a type of the condition; and a fifth logic to generate an indicator of an instruction address that generated the condition.