LOW-OVERHEAD HARDWARE PREDICTOR TO REDUCE PERFORMANCE INVERSION FOR CORE-TO-CORE DATA TRANSFER OPTIMIZATION INSTRUCTIONS

摘要

Apparatus and methods implementing a hardware predictor for reducing performance inversions caused by intra-core data transfer during inter-core data transfer optimization for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache or mid-level cache (MLC) for each core and a shared L3 or last-level cache (LLC). A hardware predictor to monitor accesses to sample cache lines and, based on these accesses, adaptively control the enablement of cache line demotion instructions for proactively demoting cache lines from lower cache levels to higher cache levels, including demoting cache lines from L1 or L2 caches (MLC) to L3 cache (LLC).

主权项

1. An apparatus comprising:
a plurality of hardware processor cores, wherein each of the hardware processor cores to include a first cache; a second cache, communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit to track accesses to a plurality of monitored cache lines in the first cache and control enablement of a cache line demotion instruction based upon the tracked accesses, wherein an execution of the cache line demotion instruction by one of the plurality of hardware processor cores to cause a plurality of unmonitored cache lines in the first cache to be moved to the second cache.