发明名称 |
AVOIDING DEADLOCKS IN PROCESSOR-BASED SYSTEMS EMPLOYING RETRY AND IN-ORDER-RESPONSE NON-RETRY BUS COHERENCY PROTOCOLS |
摘要 |
Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition. |
申请公布号 |
WO2017053086(A1) |
申请公布日期 |
2017.03.30 |
申请号 |
WO2016US50961 |
申请日期 |
2016.09.09 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
LE, Hien, Minh;TRUONG, Thuong, Quang;XU, Kun;SUBRAMANIAM GANASAN, Jaya, Prakash;RAMIREZ, Cesar, Aaron |
分类号 |
G06F12/0815;G06F9/52;G06F12/0831 |
主分类号 |
G06F12/0815 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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