| 摘要 |
Techniques are disclosed for semiconductor device wafer bonding integration. The wafer bonding integration employs device-quality embedded epitaxial layers (e.g., high-quality single-crystal semiconductor material layers) from which one or more devices (e.g., transistors) can be formed, enabling vertical 3D integration schemes. The integration techniques include the ability to produce transistors and back-end stacks on very thin substrates, where the substrate is of device-level quality. The techniques include forming a multilayer substrate including a bulk wafer, a sacrificial layer, and a device-quality layer from which one or more transistors are formed. After back-end processing, the transistors can be bonded to a host wafer that also includes transistors, such that the transistors are stacked in a vertical fashion. After the bonding process, the bulk wafer of the multilayer substrate can be removed from the transistor that was bonded, by at least partially removing the sacrificial layer of the multilayer substrate. |
