发明名称 Voltage mode sensing for low power flash memory
摘要 Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.
申请公布号 US9607708(B2) 申请公布日期 2017.03.28
申请号 US201213665409 申请日期 2012.10.31
申请人 Medtronic, Inc. 发明人 Walsh Kevin K.;Patterson Paul B.;Benton Glen W.;Wilkinson Jeffrey D.
分类号 G11C16/30;G11C7/06;G11C7/08;G11C7/22;G11C16/26;G11C16/28;G11C7/14;G11C11/00;G11C17/12;G11C29/50 主分类号 G11C16/30
代理机构 代理人 Bardell Scott A.
主权项 1. An electrically erasable flash memory, comprising: a plurality of data storage elements configured to store a plurality of data bits, each of said plurality of data bits having a data state; a reference storage element in addition to said plurality of storage elements configured to store a reference; and a voltage sensing circuit selectively coupled to individual ones of said plurality data storage elements and said reference storage element and said voltage sensing circuit being configured to bias said individual ones of said plurality of data storage elements and said reference storage element with a bias resistance and to read said data state of said individual ones of said plurality of data bits stored in said plurality of data storage elements; wherein an output of said reference from said reference storage element provides an indication that data read out from said plurality of storage elements is valid; wherein each of said plurality of data storage elements has a performance margin; wherein said voltage sensing circuit is configured to selectively bias said plurality of data storage elements with said bias being at least one of a read bias and a margin bias; and wherein, when said voltage sensing circuit biases said individual one of said plurality of data storage elements with said margin bias, said individual one of said plurality of data storage elements induces a response indicative of said performance margin of said individual one of said plurality of data storage elements.
地址 Minneapolis MN US