| 发明名称 | Memory system | ||
| 摘要 | A memory system includes: a memory controller which executes a data access process with an external device using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size. | ||
| 申请公布号 | US9606928(B2) | 申请公布日期 | 2017.03.28 |
| 申请号 | US201514630444 | 申请日期 | 2015.02.24 |
| 申请人 | KABUSHIKI KAISHA TOSHIBA | 发明人 | Eguchi Yasuyuki |
| 分类号 | G11C29/00;G06F12/0868;G06F11/10;G11C29/52;G11C7/22;G11C8/12;G11C29/04 | 主分类号 | G11C29/00 |
| 代理机构 | Holtz, Holtz & Volek PC | 代理人 | Holtz, Holtz & Volek PC |
| 主权项 | 1. A memory system comprising: a memory controller which executes a data access process with an external device using an access unit; a first memory which is connected to the memory controller via a first bus and which has a first latency; and a second memory which is connected to the memory controller via a second bus and which has a second latency longer than the first latency; wherein the access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory, and the memory controller executes a first data access process with the first memory using the first access size, and executes a second data access process with the second memory using the second access size. | ||
| 地址 | Tokyo JP | ||