| 主权项 |
1. A read/write control device of resistive type memory, including:
an address decoder for outputting at least a row selection signal and at least a column selection signal; a word line driving circuit for switching and selecting a word line according to the row selection signal outputted from the address decoder, and outputting a word line signal; a bit line driving circuit for switching and selecting a bit line according to the column selection signal outputted from the address decoder, and outputting a bit line signal; the bit line driving circuit including: at least a first logic unit, at least a first transistor set including one PMOS transistor and one NMOS transistor serially connected to each other, and a guide transistor connected to a source of the NMOS transistor of the first transistor set, wherein the first logic unit has an output terminal connected to gates of the PMOS and NMOS transistors of the first transistor set, and the first logic unit further has a pair of input terminals respectively for receiving the column selection signal and for receiving a control signal for deciding if writing data “0” is performed, and wherein drains of the PMOS and NMOS transistors of the first transistor set are connected to each other to form the bit line; a source line driving circuit for switching and selecting a source line according to the column selection signal outputted from the address decoder, and outputting a source line signal; the source line driving circuit including: at least a second logic unit, and at least a second transistor set including one PMOS transistor and one NMOS transistor serially connected to each other, wherein the second logic unit has an output terminal connected to gates of the PMOS and NMOS transistors of the second transistor set, and the second logic unit further has a pair of input terminals respectively for receiving the column selection signal and for receiving a control signal for deciding if writing data “1” is performed, and drains of the PMOS and NMOS transistors of the second transistor set are connected to each other to form the source line; at least a memory bit cell including a variable resistance element and a third transistor serially connected to each other, wherein a source of the third transistor is connected to the source line, and the variable resistance element has an end connected to a drain of the third transistor and another end connected to the bit line, and wherein a gate of the third transistor is for receiving the word line signal outputted from the word line driving circuit; and a read detection unit having a sense amplifier, wherein an input terminal of the sense amplifier is connected to a global bit line of the bit line driving circuit; when the second logic unit receives a control signal that determines writing data “1” is not to be performed and receives the column selection signal, and the first logic unit receives a control signal that determines writing data “0” is not to be performed and receives the column selection signal, a read current path goes from the global bit line connected to the input terminal of the sense amplifier, through one of the transistors of the first transistor set connected to the first logic unit that receives the column selection signal, through a memory bit cell that is selected by the address decoder, to one of the transistors of the second transistor set connected to the second logic unit that receives the column selection signal and to ground. |
