| 主权项 |
1. A driving circuit, comprising:
at least two driving units arranged in an array and coupled with each other, a first driving unit of the at least two driving units utilized to receive at least one second sub signal of a second driving signal set which is generated by a second driving unit, and to generate a first driving signal set, wherein the second driving unit is a driving unit except the first driving unit in the at least two the driving units; wherein the driving unit comprises:
a control unit utilized to control an output of a stage transmission signal according to forward and reverse scanning signals;a stage transmission signal latch unit utilized to receive the stage transmission signal and to latch the stage transmission signal for generating a latch signal;a first scanning signal generation unit utilized to generate a first scanning signal;a second scanning signal generation unit utilized to generate a second scanning signal;a first inverted output unit utilized to invert the first scanning signal and generate an inverted first scanning signal; anda second inverted output unit utilized to invert the second scanning signal generate an inverted second scanning signal; the control unit comprising a first stage transmission signal input terminal, a second stage transmission signal input terminal, a first switch control signal input terminal, a second switch control signal input terminal, and a first stage transmission signal output terminal; the control unit further comprising:
a first TFT comprising a first gate, a first source, and a first drain, the first gate coupled to the first switch control signal input terminal, the first source coupled to the first stage transmission signal input terminal, the first drain coupled to the first stage transmission signal output terminal, the first TFT utilized to control an output of a first stage transmission signal of the first stage transmission signal input terminal according to a first switch control signal provided by the first switch control signal input terminal;a second TFT comprising a second gate, a second source, and a second drain, the second gate coupled to the first switch control signal input terminal, the second source coupled to the second stage transmission signal input terminal, the second drain coupled to the first stage transmission signal output terminal, the second TFT utilized to control an output of a second stage transmission signal of the second stage transmission signal input terminal according to the first switch control signal;a third TFT comprising a third gate, a third source, and a third drain, the third gate coupled to the second switch control signal input terminal, the third source coupled to the first stage transmission signal input terminal, the third drain coupled to the first stage transmission signal output terminal, the third TFT utilized to control the output of the first stage transmission signal according to a second switch control signal provided by the second switch control signal input terminal; anda fourth TFT comprising a fourth gate, a fourth source, and a fourth drain, the fourth gate coupled to the second switch control signal input terminal, the fourth source coupled to the second stage transmission signal input terminal, the fourth drain coupled to the first stage transmission signal output terminal, the fourth TFT utilized to control the output of the second stage transmission signal according to the second switch control signal; the stage transmission signal latch unit comprising a first clock signal input terminal, a third stage transmission signal input terminal, and a latch signal output terminal; the stage transmission signal latch unit further comprising:
a first inverter comprising a first inverted input terminal and a first inverted output terminal, the first inverted input terminal coupled to the first clock signal input terminal, the first inverted input terminal utilized to receive a first clock signal;a second inverter comprising a second inverted input terminal and a second inverted output terminal, the second inverted input terminal coupled to the first inverted output terminal, the second inverter further coupled to the third stage transmission signal input terminal and the latch signal output terminal;a third inverter comprising a third inverted input terminal and a third inverted output terminal, the third inverted input terminal coupled to the first clock signal input terminal, the third inverter further coupled to the third stage transmission signal input terminal and the latch signal output terminal, the third inverted input terminal utilized to receive the first clock signal; anda fourth inverter comprising a fourth inverted input terminal and a fourth inverted output terminal, the fourth inverted input terminal coupled to the third inverted output terminal and the second inverted output terminal, the fourth inverted output terminal coupled to the latch signal output terminal. |
