发明名称 |
Detecting defective connections in stacked memory devices |
摘要 |
A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection. |
申请公布号 |
US9607716(B2) |
申请公布日期 |
2017.03.28 |
申请号 |
US201414248480 |
申请日期 |
2014.04.09 |
申请人 |
Internatiional Business Machines Corporation |
发明人 |
Kilmer Charles A.;Maule Warren E.;Sethuraman Saravanan |
分类号 |
G11C11/412;G11C11/413;G11C29/50;G11C29/00;G11C29/02;H01L23/538;H01L25/065;H01L23/48;H01L23/498;H01L23/00;H01L25/18 |
主分类号 |
G11C11/412 |
代理机构 |
Wood, Herron & Evans, LLP |
代理人 |
Wood, Herron & Evans, LLP ;Williams Robert R. |
主权项 |
1. A stacked memory device comprising:
a plurality of memory chips each having a plurality of memory locations, a plurality of bit lines and a plurality of word lines; and, a logic chip having electrical connections to, and located beneath, each of the plurality of memory chips, and designed to:
write a write data value into a location of the plurality of memory locations in a memory chip of the plurality of memory chips;read a read data value from the location in the memory chip;detect a bit error in the read data value;record a bit number corresponding to a detected bit error; and,replace a defective connection between at least one of the plurality of memory chips and the logic chip, with a spare connection. |
地址 |
Armonk NY US |