Delay lock loop

摘要

A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.

主权项

1. A delay lock loop, comprising:
a selection unit receiving a non-inverted clock signal and an inverted clock signal and generating a first clock signal and a second clock signal according to an indication signal; a buffer unit coupled to the selection unit and processing an input clock signal to generate the non-inverted clock signal and the inverted clock signal; a delay unit coupled to the selection unit, wherein the delay unit comprises a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor; and a phase detection unit coupled to the delay unit and the selection unit and generating the indication signal according to a phase difference between the second and third clock signals, wherein the delay unit adjusts the delay factor according to the indication signal.