Low power optimizations for a floating point multiplier

摘要

Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device further includes a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the programmable integrated circuit device.

主权项

1. A configurable specialized processing block on an integrated circuit device, the configurable specialized processing block comprising:
a first multiplier that generates a first partial product associated with a first set of bit locations; a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations; a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the configurable specialized processing block; a compressor tree that combines the first partial product and the second partial product to generate a multiplication result that is less precise when the first multiplier is deactivated compared to when the first multiplier is not deactivated; and a multiplexer that directly receives a portion of the second partial product, including the most significant bit of the second partial product, via a route that bypasses the compressor tree.