PLL circuit and operation method

摘要

A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control oscillator (12) that generates a signal to be returned to the phase comparator (11); and a loop filter (10) that is disposed between the phase comparator (11) and the voltage control oscillator (12) and includes an adder (50) that adds outputs from a proportional path (20), a first integral path (40), and a second integral path (30). The second integral path (30) and the first integral path (40) each include a cumulative adder, a ΔΣ modulator, and an RC filter. The lock detector (36) detects a lock state, controls a gain of the first cumulative adder (42) and a bandwidth of the first RC filter (45), and switches an input to a second ΔΣ modulator (33) to a fixed value.

主权项

1. A PLL circuit comprising:
a phase comparator configured to detect a phase difference between a reference clock and a feedback clock; an oscillator configured to generate a signal to be returned to the phase comparator; and a loop filter that is disposed between the phase comparator and the oscillator and includes an adder that adds an output from a proportional path, an output from a first integral path, and an output from a second integral path, wherein the proportional path includes:
a charge pump configured to output a current according to a detection result from the phase comparator; andan analog filter that is provided after the charge pump, the first integral path includes:a first cumulative adder that has a variable gain and cumulatively adds digital signals according to the detection result from the phase comparator;a first modulator configured to modulate a signal from the first cumulative adder;a first D/A converter configured to perform a D/A conversion on a signal from the first modulator; anda first filter that has a variable bandwidth and receives an analog signal from the first D/A converter, the second integral path includes:
a second cumulative adder configured to cumulatively add the digital signals according to the detection result from the phase comparator;a second modulator configured to modulate the signal from the second cumulative adder;a second D/A converter configured to perform a D/A conversion on a signal from the second modulator; anda second filter configured to receive an analog signal from the second D/A converter, and the PLL circuit further comprises a lock detector that detects a lock state, controls the gain of the first cumulative adder and the bandwidth of the first filter according to a detection result of the lock state, and switches an input to the second modulator to a fixed value.