Timing driven clock tree synthesis

摘要

This application discloses performing a static timing analysis on a circuit design with an unbalanced clock tree, for example, to determine data arrival timing and clock arrival timing at multiple clock-driven circuits in a circuit design, and then performing clock tree synthesis on the circuit design to initially balance the unbalanced clock tree based, at least in part, on the data arrival timing relative to the clock arrival timing at the multiple clock-driven circuits. The clock tree after initial balancing includes a clock signal path configured to provide a clock signal to each of the multiple clock-driven circuits with a new clock arrival timing that corresponds to the data arrival timing.

主权项

1. A method comprising:
determining, by a computing system, data arrival timing and clock arrival timing at multiple clock-driven circuits in a circuit design describing at least a portion of an electronic device; and performing, by the computing system, clock tree synthesis (CTS) on the circuit design, which synthesizes an unbalanced clock tree for the circuit design and utilizes the data arrival timing relative to the clock arrival timing at the multiple clock-driven circuits to initially balance the unbalanced clock tree for the circuit design, wherein the initial balancing of the unbalanced clock tree alters a clock signal path in the unbalanced clock tree to provide a clock signal to each of the multiple clock-driven circuits with a new clock arrival timing that is synchronized with the data arrival timing for the multiple clock-driven circuits, and wherein the electronic device is capable of being manufactured based, at least in part, on the circuit design.