发明名称 |
Method for manufacturing a semiconductor device |
摘要 |
The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed. |
申请公布号 |
US9608091(B2) |
申请公布日期 |
2017.03.28 |
申请号 |
US201514921445 |
申请日期 |
2015.10.23 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
Mihara Tatsuyoshi |
分类号 |
H01L21/336;H01L29/66;H01L29/423;H01L29/792;H01L27/11568;G11C11/56;G11C16/04;H01L27/11;H01L27/06;H01L21/8234 |
主分类号 |
H01L21/336 |
代理机构 |
Mattingly & Malur, PC |
代理人 |
Mattingly & Malur, PC |
主权项 |
1. A method for manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate having a main surface, the main surface including a first region for a MISFET of a memory cell and a second region for a capacitive element; (b) forming a first conductor film over the main surface of the semiconductor substrate in the first and second regions via a first insulation film; (c) after the step (b), patterning the first conductor film to form a first gate electrode of the MISFET in the first region and a first electrode of the capacitive element in the second region, the first electrode having a first pattern and a second pattern which are opposed to each other in a sectional view; (d) after the step (c), forming a second insulation film so as to cover a side surface of the first gate electrode of the MISFET and side surfaces of the first and second patterns of the first electrode; and (e) after the step (d), forming a second conductor film over the main surface of the semiconductor substrate in the first and second regions, thereby to form a second gate electrode of the MISFET on a surface of the second insulation film and a second electrode of the capacitive element at a space between the first and the second patterns with the second insulation film in the sectional view. |
地址 |
Tokyo JP |