Method and apparatus to prevent voltage droop in a computer

摘要

In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

主权项

1. A processor comprising:
at least one core including a first core, wherein the first core includes:
execution logic to execute one or more instructions;dispatch logic to output a plurality of instructions to the execution logic;control logic to operate in one of three possible states comprising a first state, a second state, and a third state, wherein the control logic is to:
in the first state, provide a baseline voltage to the first core;in the third state, provide a high voltage to the first core; andin the second state:
provide a middle voltage to the first core, wherein the middle voltage is higher than the baseline voltage and is lower than the high voltage;detect an onset of an instruction high power event associated with execution of a least one of the instructions;cause the dispatch logic to throttle output of the instructions to the execution logic to a first output level responsive to detection of the onset of the instruction high power event;determine a rate of throttling of the dispatch logic; andin response to a determination that the rate of throttling of the dispatch logic exceeds a threshold, transition to the third state, wherein the third state comprises ceasing throttling the output of the instructions to the execution logic; and cache memory coupled to the at least one core.