| 发明名称 | Metal line with increased inter-metal breakdown voltage | ||
| 摘要 | A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench. | ||
| 申请公布号 | US9607997(B1) | 申请公布日期 | 2017.03.28 |
| 申请号 | US201514848081 | 申请日期 | 2015.09.08 |
| 申请人 | SANDISK TECHNOLOGIES INC. | 发明人 | Yamada Katsuo;Takahashi Yuji;Fukuo Noritaka;Uozaki Masami;Shishido Kiyokazu;Futase Takuya;Watanabe Shunsuke |
| 分类号 | H01L21/76;H01L27/112;H01L21/768;H01L23/528;H01L23/522 | 主分类号 | H01L21/76 |
| 代理机构 | Foley & Lardner LLP | 代理人 | Foley & Lardner LLP |
| 主权项 | 1. A method of forming an integrated circuit comprising: forming a first metal layer; subsequently forming a dielectric layer over the first metal layer; subsequently forming a wide trench having a width W1 and forming narrow trenches having a width W2 that is less than W1 in the dielectric layer, the wide trench extending deeper in outer regions than in a central region; subsequently performing a trench modification step that changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench; and subsequently depositing a second metal layer that fills the wide trench and the narrow trenches. | ||
| 地址 | Plano TX US | ||